1. Field of the Invention
The present invention relates to an optical proximity correction (OPC) method, and more particularly, to an OPC method using dummy patterns to reduce the difference in pattern density.
2. Description of the Prior Art
In semiconductor manufacturing processes, in order to transfer an integrated circuit layout onto a semiconductor wafer, the integrated circuit layout is first designed and formed as a photo-mask pattern. The photo-mask pattern is then proportionally transferred to a photoresist layer positioned on the semiconductor wafer.
As the design pattern of integrated circuit becomes smaller and due to the resolution limit of the optical exposure tool, optical proximity effect will easily occur during the photolithographic process for transferring the photo-mask pattern with higher density. The optical proximity effect will cause defects when transferring the photo-mask pattern, such as right-angled corner rounding, line end shortening, and line width increasing/decreasing. U.S. Pat. No. 6,042,973 to Pierrat and U.S. Pat. No. 6,077,630 to Pierrat describe forming a subresolution grating composed of approximately circular contacts around the border of the primary patter of a photo-mask. As a result, resolution at the edges of the photo-mask pattern is improved when the pattern is printed on a wafer surface. However, the subresolution grating is not able to suppress the optical proximity effect when transferring the photo-mask pattern. Therefore, in order to avoid the above-mentioned defects caused by the optical proximity effect, the semiconductor process uses a computer system to perform an optical proximity correction (OPC) method of the integrated circuit layout. The corrected integrated circuit layout is then designed as a photo-mask pattern and is formed on a surface of the photo-mask.
Please refer to FIG. 1 to FIG. 4. FIG. 1 to FIG. 4 are schematic diagrams of a prior art OPC method. As shown in FIG. 1, an original integrated circuit layout 10 comprises a plurality of line FIG. 12 for defining word lines. In order to avoid the defects of line end shortening and line width increasing/decreasing caused by the optical proximity effect when transferring the line FIG. 12, a computer system is used to perform an OPC method of the integrated circuit layout 10. As shown in FIG. 2, the photo-mask pattern 14 is a result of the integrated circuit layout 10 of FIG. 1 after correcting by the prior art OPC method. As well, as shown in FIG. 3, an original integrated circuit layout 16 comprises a plurality of rectangular FIG. 18 for defining doped regions. In order to avoid the defects of right-angled corner rounding caused by the optical proximity effect when transferring the rectangular FIG. 18, a computer system is used to perform an OPC method of the integrated circuit layout 16. As shown in FIG. 4, the photo-mask pattern 20 is a result of the integrated circuit layout 16 of FIG. 3 after correcting by the prior art OPC method.
The prior art OPC method only uses one OPC model to correct the whole integrated circuit layout, and the factor of different pattern density in local regions of the photo-mask resulting in overexposure or underexposure is not taken into consideration. Furthermore, as the system on chip (SOC) is developed, many different kinds of semiconductor devices (such as memory, logic circuits, Input/Output, and central processing unit) are integrated and formed on one chip for substantially reducing costs and improving speed. Therefore, the pattern density of integrated circuit layout is very different in local regions of the chip, and the prior art OPC method is not applicable.